Sr Staff Digital Engineer - San Jose, United States

Originally posted 5 October 2026 by the employer.

About the role

As a Sr Staff Digital Engineer, you will be responsible for the architecture, design, integration, and implementation of advanced digital and mixed-signal ICs and SoCs.

What you'll do

• Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.

What you'll need

• MSEE or Ph.D. in Electrical Engineering with 8+ years of relevant industry experience, or BSEE with 12+ years of relevant industry experience.
• Strong background in digital IC and SoC architecture, design, and implementation.
• Proven experience with SoC interconnects and protocols including AHB, APB, AXI, USB, I2C/I3C, SPI, and UART.
• Strong knowledge of embedded memory architectures including SRAM, OTP, MTP, and Flash.
• Extensive hands-on experience with RTL design using Verilog/SystemVerilog.
• Experience with the complete ASIC/SoC development flow, including RTL design and simulation, SoC integration, Lint and design quality checks, CDC and RDC verification, Logic synthesis, DFT implementation, SDC constraint development, Static Timing Analysis (STA), timing closure and design signoff.
• Strong understanding of multi-clock designs, reset architecture, and low-power design methodologies.
• Experience driving technical debug and resolution of functional, timing, and silicon issues.

Nice to have

• Mixed-signal IC development experience and understanding of analog/digital integration challenges.
• Experience with industry-standard EDA tools such as Synopsys Design Compiler, PrimeTime, SpyGlass, VC Static, Verdi, and Cadence design environments.
• Hands-on experience integrating and debugging Arm® processor subsystems (Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M33, or similar Arm cores), including AHB/APB interconnects, memory subsystems, interrupt controllers, debug infrastructure, boot flows, and firmware interaction.
• Experience with high-speed interface design and implementation.
• Familiarity with FPGA prototyping and emulation flows.
• Mandarin language proficiency.

Skills: digital architecture, RTL development, SoC integration, ASIC/SoC development flow, timing closure, Verilog/SystemVerilog