Sr Staff Customer Engineer, Parasitic Extraction
Originally posted 16 September 2026 by the employer — open 2 days.
This role focuses on interconnect parasitic extraction for FinFET nodes.
About the role
This role involves leading technical engagements for interconnect parasitic extraction solutions as a Senior Staff Customer Engineer.
What you'll do
- Lead technical benchmarks for interconnect parasitic extraction on advanced FinFET nodes, demonstrating StarRC's accuracy and performance.
- Drive pre-sales engagements, including methodology presentations, live demos, and proof-of-concept evaluations.
- Manage post-sales technical relationships, serving as the primary technical point of contact for parasitic extraction workflows.
- Resolve customer issues end to end, from initial triage through R&D engagement to deployment.
- Plan and lead Technical Review Meetings and Management Review Meetings, aligning customer roadmaps with Synopsys solutions.
- Collaborate with sales, marketing, and R&D teams to define account strategies and shape product direction.
What you'll need
- Bachelor's degree in Electrical Engineering or equivalent, with 7+ years of industry experience, or Master's degree with 5+ years.
- Minimum 2 years of hands-on experience with interconnect parasitic extraction tools such as StarRC or Quickcap on advanced FinFET nodes (7nm and below).
- Strong understanding of digital and custom design flows, including how parasitic extraction fits into timing closure, signoff, and reliability analysis.
- Deep knowledge of process technology and how design rules, metal stacks, and device characteristics affect extraction accuracy and performance.
- Proficiency in at least one scripting language (TCL, Perl, or Python) for automation, debugging, and workflow customization.
Skills: parasitic extraction, StarRC, FinFET nodes, timing closure, scripting
This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
680
|
Median days open
86 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (680 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 680 |
| Open roles in the wider Physical Implementation family | 87 | 1388 · 105 employers |
| Median days open | 57 d | 86 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: parasitic extraction, StarRC, FinFET nodes, timing closure, scripting
Who's hiring in this category
- Cadence Design Systems · 173 open roles · median 141 d
- Synopsys (this employer) · 52 open roles · median 58 d
- NVIDIA · 50 open roles · median 90 d
- Micron Technology · 36 open roles · median 119 d
- Qualcomm · 36 open roles · median 72 d
- Intel Corporation · 29 open roles · median 23 d
How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.