Sr. Staff CAD- ASIC Design Verification Agentic Workflow - Santa Clara, CA, United States
$127,630 - $191,200 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
The position participates in defining the organization's design infrastructure, methodology, and workflows.
What you'll do
- Develop and deploy agentic workflows for ASIC verification activities.
- Automate regression analysis, failure triage, root-cause identification, and coverage closure.
- Build AI agents that interact with EDA tools, simulation environments, and verification databases.
- Integrate LLM-based assistants into verification flows.
- Develop workflows for test generation, assertion generation, UVM code creation, bug analysis, coverage improvement recommendations, and documentation generation.
- Develop scalable infrastructure for agent orchestration and multi-agent collaboration.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 4+ years of ASIC Design Verification experience.
- Strong expertise in SystemVerilog, UVM, Assertions (SVA), and Functional Coverage.
- Expertise in Constrained-random verification.
- Experience with Simulation-based verification, Formal verification, and Emulation/FPGA prototyping.
- Deep understanding of SoC/IP verification methodologies.
- Experience with LLMs, Agent frameworks, and prompt engineering.
- Understanding of Multi-agent systems, Autonomous planning and execution, and Tool calling and function orchestration.
- Experience with industry-standard tools such as VCS/Verdi, Xcelium/Jasper, Siemens Questa.
- Experience with Coverage and regression management tools.
- Scripting language experience.
Skills: CAD member, Agentic design verification workflow, AI agents, LLM-based assistants, EDA tools
This role has been open 1 day — well below the 50-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
56
|
Median days open
50 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (56 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 56 |
| Open roles in the wider Physical Implementation family | 17 | 1419 · 109 employers |
| Median days open | 10 d | 50 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: CAD member, Agentic design verification workflow, AI agents, LLM-based assistants, EDA tools
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 48 d
- Cadence Design Systems · 7 open roles · median 21 d
- NVIDIA · 6 open roles · median 22 d
- Qualcomm · 4 open roles · median 57 d
- Synopsys · 3 open roles · median 42 d
- Arteris · 2 open roles · median 75 d
How we counted: 56 open EDA/CAD Engineering (AI EDA Design) roles from 23 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.