Sr. Staff ASIC Verification Engineer - Sunnyvale, CA, United States
Originally posted 4 June 2026 by the employer.
About the role
As a senior member of Tensordyne’s ASIC team, you will lead all phases of ASIC verification and be responsible for the pre-silicon correctness of multi-chip silicon solutions for generative AI inference acceleration. The design integrates computational accelerator units with third-party SoC IP blocks for data center systems.
What you'll do
- Lead verification planning from architecture through tapeout, defining signoff criteria, coverage convergence, and bug tracking. - Develop block-level, subsystem, and full-chip verification environments and tests using SystemVerilog and UVM. - Verify SoC subsystems including embedded CPUs (ARM/RISC-V) and interconnects using C and assembly diagnostic validation. - Work closely with design and architecture teams to triage, debug, and resolve functional and performance issues. - Establish reusable verification methodologies, frameworks, and regression testbenches that scale from block to full-chip environments. - Mentor and technically guide verification engineers through test planning, verification closure, and post-silicon validation in the lab.
What you'll need
- 15+ years of ASIC verification experience taking multiple chips through the complete verification lifecycle and post-silicon validation. - Expertise in SystemVerilog, UVM, constrained randomization, and functional coverage. - Experience with C/C++ or System-C, along with object-oriented programming principles and coverage-driven verification. - Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM, or SerDes. - Scripting experience in Python, Perl, TCL, or shell programming. - B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related field.
Skills: ASIC verification, SystemVerilog, UVM, constrained randomization, functional coverage, PCIe
This role has been open 119 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tensordyne | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1233 |
| Open roles in the wider Digital Design & Verification family | 3 | 3298 · 115 employers |
| Median days open | 119 d | 64 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC verification, SystemVerilog, UVM, constrained randomization, functional coverage, PCIe
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.