Sr. Staff ASIC Design Engineer - CA, San Jose, United States
Originally posted 4 September 2026 by the employer.
This role supports IP development for Silicon implementation and first-time-right SW solution.
About the role
As a Sr. Staff ASIC Design Engineer, you will be a key member of AMD’s FPGA Product and Platform development team, with various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. This involves supporting IP development for Silicon implementation and first-time-right SW solution.
What you'll do
- Participate in all stages of the design flow, from RTL development through GDS implementation.
- Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
- Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
- Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
- Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
- Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.
What you'll need
- Strong understanding of different design stages from RTL to GDS implementation.
- Proficiency in RTL design implementation of Digital/Analog blocks using Verilog/System Verilog.
- Experience with HBM, D2D, Serdes, PCIe protocols.
- Knowledge in VLSI design, Design Automation, and IC design.
- Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis.
- Basic knowledge of EDA Tools (Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
- Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
Nice to have
- Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments.
- Basic understanding of FPGA architecture and customer usage model.
Skills: DFT architecture, Scan insertion, ATPG pattern generation, gate-level simulation, Mentor TestKompress
This role has been open 41 days — well below the 56-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
250
|
Median days open
56 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (250 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 250 |
| Open roles in the wider Digital Design & Verification family | 255 | 3188 · 115 employers |
| Median days open | 41 d | 56 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFT architecture, Scan insertion, ATPG pattern generation, gate-level simulation, Mentor TestKompress
Who's hiring in this category
- AMD (this employer) · 40 open roles · median 41 d
- NVIDIA · 25 open roles · median 41 d
- Qualcomm · 24 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 63 d
- Synopsys · 13 open roles · median 23 d
- Micron Technology · 11 open roles · median 54 d
How we counted: 250 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.