Sr Staff Applications Engineer - ICV Runset Development
Originally posted 13 September 2026 by the employer — open 7 days.
This role focuses on IC Validator runset development.
About the role
This role involves developing and validating DRC, LVS, and Fill runsets for the Synopsys IC Validator tool.
What you'll do
- Develop and validate DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool.
- Collaborate with foundries to understand process requirements and deliver PV runsets for advanced nodes.
- Automate qualification processes for IC Validator runsets using Perl, Tcl, and Python.
- Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
- Interface with customers and FAEs to gather requirements, provide technical support, and deploy PV solutions.
- Mentor junior team members, share best practices, and contribute to knowledge sharing.
What you'll need
- B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
- 5-10 years of hands-on experience in the Physical Verification (PV) domain.
- Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
- Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
- Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
- Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
- Exposure to competitive EDA tools and awareness of their strengths and limitations.
Skills: IC Validator, DRC, LVS, Fill runsets, rule deck files, Physical Verification
This role has been open 5 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
668
|
Median days open
86 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (668 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 668 |
| Open roles in the wider Physical Implementation family | 87 | 1373 · 107 employers |
| Median days open | 59 d | 86 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: IC Validator, DRC, LVS, Fill runsets, rule deck files, Physical Verification
Who's hiring in this category
- Cadence Design Systems · 168 open roles · median 148 d
- Synopsys (this employer) · 55 open roles · median 59 d
- NVIDIA · 46 open roles · median 64 d
- Micron Technology · 35 open roles · median 121 d
- Qualcomm · 34 open roles · median 72 d
- Intel Corporation · 29 open roles · median 25 d
How we counted: 668 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.