Sr Staff Applications Engineer, HAV Solutions - Remote
Originally posted 16 September 2026 by the employer — open 4 days.
About the role
This role involves leading technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments.
What you'll do
- Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers.
- Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems.
- Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures.
- Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures.
- Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements.
- Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums.
What you'll need
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience.
- 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation.
- Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools.
- Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture.
- Hands-on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high-speed SerDes protocols.
- Proficiency in Tcl, Python, or shell scripting for automation and flow development.
Skills: HAPS-200, ProtoCompiler, multi-FPGA systems, DDR/PCIe/HBM/SerDes IP, ASIC-to-FPGA flow
This role has been open 2 days — well below the 36-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
94
|
Median days open
36 d
|
Median salary
$157k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (94 roles · 10 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 94 |
| Median days open | 5 d | 36 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $157k |
Skills observed across this category: HAPS-200, ProtoCompiler, multi-FPGA systems, DDR/PCIe/HBM/SerDes IP, ASIC-to-FPGA flow
Who's hiring in this category
- Synopsys (this employer) · 44 open roles · median 5 d
- Cadence Design Systems · 19 open roles · median 61 d
- Renesas Electronics · 14 open roles · median 37 d
- Keysight Technologies · 6 open roles · median 67 d
- GlobalFoundries · 3 open roles · median 72 d
- AMD · 2 open roles · median 62 d
How we counted: 94 open Applications FAE (EDA Tools) roles from 10 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.