Sr Silicon Design Verification Engineer - TX, Austin, United States
Originally posted 23 September 2026 by the employer.
About the role
This role focuses on planning, developing, and executing verification activities for new and existing features within AMD’s graphics processor IP.
What you'll do
- Collaborate with architecture, hardware, and firmware teams to understand and verify new feature requirements.
- Develop verification test plans that account for interactions across hardware, firmware, software drivers, and system-level use cases.
- Develop directed and constrained-random verification tests.
- Debug test failures, identify root causes, and partner with RTL and firmware engineers to resolve design and test issues.
- Review functional and code coverage metrics and enhance verification content to achieve coverage objectives.
- Contribute to verification methodology improvements that enhance quality, efficiency, and scalability.
What you'll need
- Experience with IP-level ASIC verification.
- Experience debugging RTL and firmware using simulation and verification tools.
- Experience working with UVM-based testbenches in Linux and Windows environments.
- Knowledge of Verilog, SystemVerilog, C, and C++.
- Understanding graphics pipeline architecture and associated verification challenges.
- Experience developing UVM-based verification frameworks, methodologies, processes, and workflows.
Nice to have
- Exposure to simulation profiling, performance optimization, acceleration technologies, and HLS tools or methodologies.
- Experience using C++ within Linux environments; exposure to Windows platforms is beneficial.
- Familiarity with SystemC, TLM, and related modeling approaches.
- Experience with scripting languages such as Perl, Ruby, shell scripting, or Makefiles.
- Experience providing technical guidance, mentorship, or informal leadership within engineering teams.
- Exposure to video codec technologies, multimedia systems, or related solutions is beneficial.
Skills: verification activities, test plans, UVM-based testbenches, SystemVerilog, debug RTL, functional and code coverage
This role has been open 17 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1183
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1183 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 102 | 1183 |
| Open roles in the wider Digital Design & Verification family | 265 | 3166 · 114 employers |
| Median days open | 50 d | 64 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: verification activities, test plans, UVM-based testbenches, SystemVerilog, debug RTL, functional and code coverage
Who's hiring in this category
- Qualcomm · 105 open roles · median 44 d
- AMD (this employer) · 102 open roles · median 51 d
- NVIDIA · 73 open roles · median 65 d
- Synopsys · 61 open roles · median 27 d
- SiFive · 54 open roles · median 68 d
- Cadence Design Systems · 51 open roles · median 110 d
How we counted: 1183 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.