Sr. Semiconductor Test Engineer - Austin, TX, United States
$140,000 - $270,000 USD yearly
Originally posted 21 October 2026 by the employer.
Focus on test engineering for analog compute-in-memory AI inference processors across Wafer Sort and Final Package Test.
About the role
Mythic is hiring a Sr. Semiconductor Test Engineer to own production test across the full silicon lifecycle, from bring-up and characterization through Wafer Sort, Final Package Test, and high-volume manufacturing. The role focuses on AI inference processors based on analog compute-in-memory architecture.
What you'll do
- Own production test strategy across Wafer Sort, Final Package Test, characterization, screening, and volume ramp. - Develop, debug, optimize, and release production test programs for new silicon products. - Execute silicon bring-up, characterization, correlation, guardbanding, and test transfer into manufacturing. - Drive yield and quality analysis by identifying systematic failures and escapes to root cause. - Collaborate with OSATs, foundries, and ATE vendors to deploy and sustain production test flows. - Build infrastructure, automation, and analytics for production test and yield learning.
What you'll need
- 5+ years of experience in semiconductor test engineering, product engineering, or production test development. - Hands-on ownership of Wafer Sort and Final Package Test. - Proven experience developing, debugging, and releasing test programs on ATE platforms in production. - Experience converting and translating test patterns from STIL, WGL, and VCD into ATE-specific pattern formats. - Solid grounding in manufacturing test flows, device screening, test coverage, guardbanding, and outgoing quality. - Experience taking silicon through bring-up, characterization, yield ramp, and production release.
Nice to have
- Experience testing mixed-signal or analog silicon, including trim and calibration. - Experience with AI, accelerator, or high-performance compute silicon. - Experience with Advantest, Teradyne, or similar ATE platforms. - Experience with probe cards, load boards, hardware interfaces, and test hardware debug. - Knowledge of DFT structures such as scan, MBIST, and boundary scan. - Experience managing OSATs and external manufacturing partners, as well as scripting and test-data analysis with Python, JMP, or yield-analysis tools.
This role has been open 0 days — well below the 33-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
556
|
Median days open
33 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Mythic | All employers we track in this specialty (556 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 556 |
| Open roles in the wider Silicon Validation & Test family | 3 | 2244 · 112 employers |
| Median days open | 0 d | 33 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 79 open roles · median 27 d
- Renesas Electronics · 44 open roles · median 27 d
- Infineon Technologies · 43 open roles · median 41 d
- Micron Technology · 28 open roles · median 37 d
- Qualcomm · 28 open roles · median 33 d
- Texas Instruments · 24 open roles · median 28 d
How we counted: 556 open Silicon Test Engineering (DFT Test) roles from 77 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.