Sr. RTL Design Engineer - CA, San Jose, United States
Originally posted 24 September 2026 by the employer.
About the role
This role involves technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization, leveraging modern RTL design methodologies, advanced EDA tools, and AI-driven automation for IP development and first-time-right SW solution.
What you'll do
- Participate in all stages of the design flow, from RTL development through GDS implementation.
- Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
- Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
- Collaborate with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
- Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools.
What you'll need
- Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
- Strong RTL design and integration experience using Verilog and SystemVerilog.
- Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
- Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
- Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
- Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
- Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
- Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
- Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
- Bachelor's or master’s degree in electrical engineering, computer engineering, or a related field.
Nice to have
- Familiarity with FPGA architectures and prototyping methodologies is a plus.
This role has been open 16 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1019
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1019 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 75 | 1019 |
| Open roles in the wider Digital Design & Verification family | 265 | 3166 · 114 employers |
| Median days open | 31 d | 60 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 60 d
- Synopsys · 86 open roles · median 24 d
- AMD (this employer) · 73 open roles · median 34 d
- Analog Devices · 50 open roles · median 41 d
- NXP Semiconductors · 48 open roles · median 78 d
- NVIDIA · 46 open roles · median 64 d
How we counted: 1019 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.