Sr. Principal Test Engineer - Westlake Village, CA, United States
Verification, Validation & Test
Originally posted 2 October 2026 by the employer.
About the role
This role is responsible for independently leading test and development for Marvell analog & Sipho products across all phases of new product introduction.
What you'll do
- Lead test engineering solutions across all phases of new silicon bring-up, product sampling, qualification, characterization and high-volume manufacturing at OSATs.
- Own all aspects of the test solution, including software, tester equipment, PCBs, mechanical fixturing, probe hardware and sockets.
- Drive test time reduction and yield improvements in partnership with Product Engineering to meet manufacturing targets.
- Implement highly robust and automated test processes to guarantee product quality.
- Work with Design and Product Engineering to improve product test coverage at wafer-probe and package levels.
- Provide necessary test engineering support for all customer returns working laterally with Quality engineering.
What you'll need
- Bachelor or Master of Science degree in Electrical Engineering, or related field.
- 10 years experience with RF/Mixed-Signal/Sipho IC test, with a focus on hardware and software design, yield improvement, test time reduction, and manufacturing process improvements.
- Skill in software automation for semiconductor test using bench instruments (GPIB/Ethernet), PXI instrumentation, or standard ATE testers (Advantest, Teradyne).
- Strong familiarity in one or more of the following languages: Python, C, CVI, Labview.
Nice to have
- Good understanding of linear/limiting high-speed TIA’s and Drivers and their test and characterization using RF test equipment.
- Hands-on wafer sort and handler experience for analog devices up to 67GHz.
- Familiarity with de-embedding techniques for microwave test setups.
- Strong familiarity with test bench equipment, including Network Analyzers, Sampling Oscilloscopes, Power Supplies and Power Meters.
- Experience with schematic capture, PCB layout, and 2D/3D CAD software for design review.
Market context
This role has been open 0 days — well below the 22-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
506
|
Median days open
22 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (506 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 506 |
| Open roles in the wider Silicon Validation & Test family | 49 | 2172 · 110 employers |
| Median days open | 10 d | 22 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 58 open roles · median 14 d
- Infineon Technologies · 40 open roles · median 35 d
- Renesas Electronics · 35 open roles · median 29 d
- AMD · 28 open roles · median 29 d
- Micron Technology · 27 open roles · median 31 d
- Qualcomm · 26 open roles · median 15 d
How we counted: 506 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.