Sr. Principal Product Engineer - San Jose, United States
$161,000 - $299,000 USD yearly
Originally posted 11 September 2026 by the employer.
This Sr. Principal Product Engineer will be a technical leader on the Voltus product engineering team, focusing on power noise and reliability analysis.
About the role
This Sr. Principal Product Engineer will be a technical leader on the Voltus product engineering team, working on Cadence’s power noise and reliability analysis platform. The role sits between strategic customers/foundries, Applications, and R&D, and is accountable for turning IR/EM, PDN, and electrothermal signoff requirements into product and flow solutions.
What you'll do
- Serve as the primary technical interface to R&D for Voltus, driving product requirements, priorities, and methodology for strategic foundry and customer programs.
- Lead Voltus enablement for advanced-node IR/EM signoff: flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment.
- Own resolution of complex customer issues spanning static/dynamic IR, EM, low-power / multi-voltage domains, hierarchical and full-chip signoff, and related timing/stack-die interactions.
- Define and validate foundry-aligned power integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams on advanced-node and 3DIC readiness.
- Influence product roadmap including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis based on foundry and customer gaps.
- Mentor Lead/Principal PEs and AEs; set debug standards, deployment practices, and issue-tracking discipline for the account/foundry program.
What you'll need
- Bachelor’s in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years.
- Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows.
- Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff.
- Proven ability to separate critical issues from noise, debug large SoC/PDN problems, and close the loop from customer requirement to R&D fix to deployment.
- Scripting in Tcl and Python.
Nice to have
- Direct experience with Voltus and adjacent Cadence digital signoff/implementation tools (Integrity, Tempus, Innovus, Quantus/QRC).
- 3DIC / chiplet, electrothermal, and advanced FinFET or GAA node experience.
- Prior technical leadership of PE/AE teams or of a strategic account/foundry program.
Skills: Voltus, IR/EM signoff, PDN, physical implementation, foundry enablement
This role has been open 33 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 155 | 688 |
| Open roles in the wider Physical Implementation family | 178 | 1469 · 108 employers |
| Median days open | 168 d | 78 d (+90 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: Voltus, IR/EM signoff, PDN, physical implementation, foundry enablement
Who's hiring in this category
- Cadence Design Systems (this employer) · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.