Sr. Principal IC Digital Flow AE - San Jose, United States
$148,400 - $275,600 USD yearly
Originally posted 8 October 2026 by the employer.
About the role
As an expert Digital Implementation and Signoff Field Applications Engineer, you will work with customers to deploy Cadence technologies in Synthesis, P&R, and Signoff. You will also work directly with the Cadence R&D group to drive customer requirements and influence the direction of Cadence products.
What you'll do
- Provide technical support to Cadence customers in Backend Digital Design Implementation and Signoff, including Place and Route, Design Closure, and timing/power signoff.
- Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules.
- Drive technical evaluations/benchmarks to success.
- Work closely with R&D to enhance tools and methodologies to meet and exceed customer requirements.
- Drive adoption and proliferation of Cadence tools and technologies.
- Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
What you'll need
- 10+ years of industry Physical Design experience.
- BS degree in Computer Science/Engineering, Electrical, Engineering, or related field.
- Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
- Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure.
- Experience with advanced nodes 10nm and below.
- Experience in scripting languages such as Tcl/Perl/Python.
- Strong customer-facing communication and problem-solving skills.
Nice to have
- MS degree Computer Science/Engineering, Electrical, Engineering, or related field.
- Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking.
- Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime.
- Experience with advanced nodes 5nm and below.
Skills: digital implementation flows, P&R, timing/power signoff, Cadence tools, Tcl/Perl/Python
This role has been open 0 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 163 | 704 |
| Open roles in the wider Physical Implementation family | 187 | 1495 · 107 employers |
| Median days open | 162 d | 79 d (+83 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: digital implementation flows, P&R, timing/power signoff, Cadence tools, Tcl/Perl/Python
Who's hiring in this category
- Cadence Design Systems (this employer) · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology · 44 open roles · median 107 d
- Qualcomm · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.