Sr Principal Engineer -SIPI - San Jose, United States
$154,000 - $286,000 USD yearly
Originally posted 31 July 2026 by the employer — open 41 days.
About the role
This role involves being a key contributor to advanced high-speed IP products within the HPP IP R&D Group. You will focus on SI/PI optimization and verification for test chip package designs and evaluation boards.
What you'll do
- Work on test chip package design SI/PI optimization and verification.
- Work on evaluation board design optimization for SI/PI performance.
- Provide extracted and measured channel models for chip designers.
- Support customer inquiries and provide guidelines for package and PCB SI/PI design.
- Review customer package and board designs and simulation results.
- Perform link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
- Assist with SI/PI related debug of test chips or customer ASICs in the lab.
What you'll need
- M.S. or Ph.D. Electrical Engineering (or similar degree).
- 3+ years of experience working with high speed SerDes and PHYs.
- Good understanding of high speed SerDes architecture.
- Hands on lab experience with high speed oscilloscopes, TDRs, VNAs, spectrum analyzers.
- Fluency with 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave.
- Experience with IBIS-AMI model simulations.
- Experience with simulation result to lab measurement correlation.
- Good understanding of PCB and FCBGA design rules and requirements.
Skills: SI/PI optimization, SerDes, high-speed oscilloscopes, TDRs, Sigrity/Clarity, IBIS-AMI
This role has been open 153 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI optimization, SerDes, high-speed oscilloscopes, TDRs, Sigrity/Clarity, IBIS-AMI
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.