Sr. Principal Engineer, Design Technologist - Richardson, Texas, United States of America, United States
$171,000 - $296,000 USD yearly
Originally posted 22 May 2026 by the employer.
About the role
This role focuses on enabling efficient silicon development by aligning SoC design methodologies with foundry process technologies, improving power, performance, and area (PPA), and supporting manufacturability. You will interface with fab and process teams to translate process technology capabilities, design rules, and constraints into design guidelines and optimized EDA flows.
What you'll do
- Interface with fab and process teams to translate technology node constraints and design rules into design guidelines, DFM practices, and yield optimization. - Drive technology benchmarking, define figure-of-merit (FOM) analysis across technology nodes, and evaluate process node options for SoC products. - Collaborate across architecture, RTL, and physical design teams to define technology-aware design methodologies and sign-off flows. - Develop and enhance EDA flows for advanced process nodes across synthesis, P&R, timing closure, power optimization, and sign-off verification. - Partner with internal methodology groups and EDA tool vendors to integrate new methodologies and guide tool roadmaps. - Provide technical guidance, mentor engineers, and support customers and partners on design technology, PPA, and process node topics.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - Minimum 15 years of experience in SoC design, physical design, EDA flows/methodologies, or semiconductor process integration. - Deep understanding of semiconductor fabrication processes on advanced process nodes, technology PDKs, and technology development/fab interactions. - Hands-on experience with timing, power, and signal integrity trade-offs in modern SoCs, along with a track record of developing SoC implementation flows that impact PPA. - Working knowledge of industry-standard EDA tools for design and simulation such as Cadence, Synopsys, or Siemens.
Nice to have
- Experience working with yield analysis and silicon bring-up. - Experience in advanced packaging or chiplet architecture.
Skills: Fab and Process interface, technology nodes, design rules, PPA, DFM, yield optimization, EDA
This role has been open 222 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 704 |
| Open roles in the wider Physical Implementation family | 47 | 1513 · 111 employers |
| Median days open | 28 d | 70 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Fab and Process interface, technology nodes, design rules, PPA, DFM, yield optimization
Who's hiring in this category
- Cadence Design Systems · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology · 45 open roles · median 55 d
- GlobalFoundries (this employer) · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.