Sr Principal CAD & HPC Workflow - San Jose, CA, United States
$197,000 - $346,000 USD yearly
Originally posted 7 October 2026 by the employer.
About the role
This role involves shaping the engineering environment for Memory product development, spanning DRAM, HBM, NAND, and custom memory programs. It focuses on modernizing and scaling platforms that global design teams utilize daily, from CAD software infrastructure to compute workload scalability.
What you'll do
- Serve as a senior engineer partnering with the CAD Software and HPC teams to support global Memory design teams.
- Develop improvement and quality metrics for job management and workflow performance.
- Establish customer-facing service levels with dashboards and reporting for continuous improvement.
- Shape CAD software architecture, Git/Bitbucket repositories, Jenkins automation, CI/CD workflows, and project setup infrastructure.
- Collaborate with HPC teams on LSF, compute infrastructure, storage systems, and engineering workload scalability.
- Contribute to EDA infrastructure strategy and technical engagement with Cadence, Synopsys, Siemens, and other industry vendors.
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 15+ years of experience in semiconductor CAD, EDA, engineering infrastructure, or software development.
- 5+ years of engineering management experience leading technical teams.
- Strong hands-on knowledge of design infrastructure, revision control systems, software development, and engineering workflows.
- Experience driving cross-functional initiatives across design, CAD, IT, HPC, and vendor organizations.
Nice to have
- Experience with Perforce, IPLM/Methodics, Jenkins, Git, Bitbucket, and enterprise software platforms.
- Experience supporting LSF, HPC, cloud, storage, and compute infrastructure for semiconductor design environments.
- Experience with Cadence, Synopsys, and Siemens EDA ecosystems.
- Experience leading AI, agentic software, or engineering productivity initiatives.
Skills: CAD software, HPC, design automation, EDA vendors, workflow
This role has been open 2 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 704 |
| Open roles in the wider Physical Implementation family | 72 | 1488 · 107 employers |
| Median days open | 101 d | 79 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: CAD software, HPC, design automation, EDA vendors, workflow
Who's hiring in this category
- Cadence Design Systems · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology (this employer) · 44 open roles · median 107 d
- Qualcomm · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.