Sr. Module Engineer, Hybrid Bonding - Santa Clara, CA, United States
Process & Device Engineering
$147,000 - $202,500 USD yearly
Originally posted 17 September 2026 by the employer — open 2 days.
This role focuses on developing and scaling hybrid bonding technologies for advanced semiconductor packaging applications.
About the role
What you'll do
- Develop and optimize die-to-wafer (D2W) hybrid bonding processes for advanced packaging.
- Establish process windows for surface preparation, plasma activation, die placement, and alignment.
- Drive Cu-Cu and dielectric-dielectric interconnect formation focusing on electrical performance and reliability.
- Support integration of hybrid bonding into Memory architectures, Chiplet-based systems, and Co-packaged optics (CPO).
- Identify root causes of bond voids, die shift, overlay errors, and particle contamination.
- Drive bonding quality characterization using CSAM, X-ray inspection, FIB/SEM, AFM, optical metrology, and electrical test structures.
- Work with equipment engineering teams on hybrid bonding systems, die placement tools, and plasma activation modules.
- Define and execute reliability test plans, including thermal cycling, HTOL, and mechanical pull/shear testing.
- Lead cross-functional projects from concept through technology transfer.
What you'll need
- M.S. or Ph.D. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Physics, or Semiconductor Manufacturing.
- Minimum 5+ years of semiconductor process development experience after graduate degree.
- Direct experience in Hybrid bonding, Thermocompression bonding, Wafer bonding, Advanced packaging, HBM development, Cu interconnect technology, or Chiplet integration.
- Strong understanding of Cu-Cu interconnect formation, surface chemistry and plasma activation, CMP and planarization, defect engineering, and semiconductor process integration.
- Experience with DOE and JMP/Minitab analysis tools.
- Familiarity with metrology and failure analysis techniques.
Nice to have
- Ph.D. with 5+ years industry experience.
- Experience in HBM or 3D stacking technologies.
- Experience with Hybrid bonding equipment development, Direct bonding interconnect (DBI), Die placement systems, or Advanced packaging process integration.
- Knowledge of AI/HPC packaging architectures.
- Experience working with 200 mm and 300 mm wafer manufacturing environments.
- Track record of patents, publications, or conference presentations (ECTC, IEEE, IMAPS, SEMI).
Market context
This role has been open 2 days — well below the 57-day median for Process Integration roles.
Process Integration · Advanced Packaging
|
Open roles in category
69
|
Median days open
57 d
|
Median salary
$175k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Applied Materials | All employers we track in this specialty (69 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 69 |
| Open roles in the wider Process, Fab & Equipment family | 1078 | 9314 · 108 employers |
| Median days open | 26 d | 57 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $175k |
Who's hiring in this category
- Micron Technology · 13 open roles · median 103 d
- GlobalFoundries · 10 open roles · median 89 d
- Intel Corporation · 10 open roles · median 29 d
- Applied Materials (this employer) · 8 open roles · median 26 d
- Renesas Electronics · 5 open roles · median 65 d
- Lumilens · 4 open roles · median 44 d
How we counted: 69 open Process Integration (Advanced Packaging) roles from 20 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.
Santa Clara, CA, United States
On-site
$147,000 - $202,500 USD yearly
18 days ago