Sr Manager ASIC Sustaining, Silicon Operations - Sunnyvale, California, United States
Originally posted 31 August 2026 by the employer.
About the role
This role involves leading ASIC sustaining engineering efforts, focusing on the transition of chips from tape-out to final product and optimizing yield.
What you'll do
- Partner with Design, Marketing, and Sales teams to align product roadmaps with market demands.
- Transition chips from tape-out to final product, including validation, characterization, and debugging.
- Analyze wafer fabrication data and test results to improve chip yield.
- Manage relationships with foundries and Outsourced Semiconductor Assembly and Test (OSAT) partners.
- Drive process and yield maturity.
- Collaborate on design-for-test (DFT) initiatives and test cost reduction.
What you'll need
- Experience in ASIC Sustaining Engineering.
- Track record developing and executing strategy while maintaining design quality standards.
- Experience working in new and ambiguous environments.
- Ability to solve complex problems with a broad range of cross functional stakeholders.
- Ability to build and lead global teams across Yield & Test engineering.
- Eligibility to work under U.S. export control laws (U.S. citizen, national, permanent resident, refugee, or asylee).
Skills: ASIC Sustaining, Yield Enhancement & Optimization, wafer fabrication data, test results, chip yield, design-for-test (DFT)
This role has been open 44 days — well below the 54-day median for Product Engineering roles.
Product Engineering · Yield Engineering
|
Open roles in category
115
|
Median days open
54 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (115 roles · 35 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 115 |
| Open roles in the wider Silicon Validation & Test family | 12 | 2223 · 112 employers |
| Median days open | 32 d | 54 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: ASIC Sustaining, Yield Enhancement & Optimization, wafer fabrication data, test results, chip yield, design-for-test (DFT)
Who's hiring in this category
- Micron Technology · 17 open roles · median 85 d
- Infineon Technologies · 13 open roles · median 49 d
- Texas Instruments · 11 open roles · median 63 d
- onsemi · 8 open roles · median 42 d
- Renesas Electronics · 8 open roles · median 26 d
- AMD · 6 open roles · median 54 d
How we counted: 115 open Product Engineering (Yield Engineering) roles from 35 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.