Sr. Fellow -- Memory PHY Architect - CA, Santa Clara, United States
$209,000 - $230,000 USD yearly
Originally posted 26 December 2025 by the employer.
Architect advanced Memory PHY solutions covering DDR, LPDDR, GDDR, and HBM in advanced CMOS technologies.
About the role
As a key architect within the AMD Circuit Technology Design Group, you will define and guide the architecture and delivery of Memory PHY solutions in advanced CMOS technologies. The focus is on setting technical direction, guiding critical design decisions, and enabling teams to deliver mixed-signal IP across future SoCs.
What you'll do
- Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction. - Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM. - Guide high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity. - Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide. - Influence design quality and execution through design reviews, technical mentorship, and tradeoff decisions. - Support post-silicon bring-up, validation, characterization, optimization, and product readiness.
What you'll need
- Typically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design. - Degree in Electrical Engineering or related field, or equivalent professional experience. - Experience with high-speed analog and mixed-signal design, memory protocols, and system-level considerations. - Understanding of advanced CMOS technologies and modern design methodologies. - Technical background in high-speed I/O circuit design, power integrity, and signal integrity.
Nice to have
- Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes. - Experience owning or shaping architecture across multiple successful tape-outs. - Advanced degree in Electrical Engineering or related field.
Skills: Memory PHY, DDR, LPDDR, GDDR, HBM, high-speed I/O circuit
This role has been open 217 days — well above the 73-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
73 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (244 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 37 | 1453 · 106 employers |
| Median days open | 45 d | 73 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: Memory PHY, DDR, LPDDR, GDDR, HBM, high-speed I/O circuit
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD (this employer) · 27 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 139 d
- Qualcomm · 21 open roles · median 68 d
- Micron Technology · 14 open roles · median 41 d
- Apple · 9 open roles · median 27 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.