Sr. Engineer, Layout Design - Santa Clara, CA, United States
$124,920 - $171,770 USD yearly
Originally posted 25 August 2026 by the employer.
About the role
The Senior Layout Design Engineer will lead top-chip and block-level layout and perform custom Analog Layout Design for CMOS and BiCMOS circuits.
What you'll do
- Lead and perform custom analog layout design at the chip, functional block, block, sub-block, leaf cell, and standard cell levels for CMOS and BiCMOS circuits.
- Execute schematic-driven layout design while adhering to design constraints.
- Develop top-chip and block-level floor plans, power distribution networks, shielding structures, and device-matching layouts.
- Verify layouts and ensure successful DRC, LVS, and ERC signoff.
- Own chip-level integration, verification, and tape-out activities.
- Train and mentor junior layout engineers and offshore layout contractors.
What you'll need
- BA/BS degree in Layout Design or a related field, or equivalent experience.
- 15+ years of experience in layout design for analog and full-custom digital blocks.
- Experience with TSMC 180nm, 65nm, 22nm process technologies.
- Proficiency with layout editing tools in the Cadence Virtuoso design environment.
- Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre.
- Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation.
- Experience with chip-level floorplanning and analog block integration.
- Experience with chip-level integration, verification, and tape-out.
Nice to have
- Ability to use productivity-enhancing tools and design scripts to automate and improve workflow efficiency.
Skills: custom analog layout, DRC, LVS, ERC, Cadence Virtuoso, chip-level floorplanning
This role has been open 50 days — well below the 174-day median for Physical Design roles.
Physical Design · Digital Backend
|
Open roles in category
38
|
Median days open
174 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (38 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 38 |
| Open roles in the wider Physical Implementation family | 6 | 1459 · 108 employers |
| Median days open | 67 d | 174 d (−107 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: custom analog layout, DRC, LVS, ERC, Cadence Virtuoso, chip-level floorplanning
Who's hiring in this category
- Intel Corporation · 4 open roles · median 84 d
- Qualcomm · 4 open roles · median 93 d
- Micron Technology · 3 open roles · median 134 d
- Altera · 2 open roles · median 210 d
- Analog Devices · 2 open roles · median 196 d
- Lightmatter · 2 open roles · median 213 d
How we counted: 38 open Physical Design (Digital Backend) roles from 22 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.