Sr. Engineer, Layout Design - Shinagawa, Tokyo, Japan
Analog & Mixed-Signal Design
Originally posted 24 June 2026 by the employer — open 78 days.
About the role
This role involves leading top-level chip-planning and performing block-level custom layouts for CMOS and BiCMOS circuits.
What you'll do
- Lead top-level chip-planning and perform custom layouts for CMOS and BiCMOS circuits.
- Review and coordinate work content performed by offshore layout designers.
- Train junior layout engineers and offshore layout contractors.
- Perform schematic-driven layout and design constraints.
- Verify layouts, passing DRC, LVS, and ERC.
- Perform chip-level integration, verifications, and tape-out.
What you'll need
- 10 years of experience with layout design for analog and full-custom digital blocks.
- Experience with TSMC 180nm, 65nm, 22nm process technologies.
- Proficient in using layout editing tools in the Cadence Virtuoso design environment.
- Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre.
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation.
- Experience in chip-level floor planning and analog block integration.
Nice to have
- Ability to use productivity-enhancing tools and design scripts to further automate tasks.
Skills: Custom layouts, CMOS and BiCMOS circuits, Cadence Virtuoso, DRC/LVS/ERC, chip-level integration
Market context
This role has been open 78 days — well above the 66-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
259
|
Median days open
66 d
|
Median salary
$156k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (259 roles · 46 employers) |
|---|---|---|
| Open roles in category | 3 | 259 |
| Median days open | 48 d | 66 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $156k |
Skills observed across this category: Custom layouts, CMOS and BiCMOS circuits, Cadence Virtuoso, DRC/LVS/ERC, chip-level integration
Who's hiring in this category
- Micron Technology · 33 open roles · median 45 d
- Texas Instruments · 30 open roles · median 111 d
- NXP Semiconductors · 15 open roles · median 65 d
- Renesas Electronics · 14 open roles · median 53 d
- onsemi · 13 open roles · median 111 d
- Semtech · 11 open roles · median 83 d
How we counted: 259 open Analog IC Design (Analog Design) roles from 46 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.