(Sr. Engineer / Engineer) HSIF Analog Engineer - Japan
Originally posted 4 February 2026 by the employer — open 218 days.
About the role
This role is for an entry-level High-Speed Interface (SerDes) Engineer to contribute to product programs and feasibility studies.
What you'll do
- Execute circuit/system simulations and basic analyses for assigned SerDes related blocks.
- Support block integration and verification activities in collaboration with analog/digital/layout teams.
- Assist with silicon bring-up and lab characterization by preparing setups, collecting data, and supporting debug and simulation-to-measurement correlation.
- Maintain clear documentation (assumptions, checklists, reports) and contribute to technical reviews.
What you'll need
- 5 years of experience as an analog design engineer.
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent practical experience).
- Solid understanding of circuits and/or digital design fundamentals (devices, amplifiers, feedback, sampling, timing, basic signal integrity concepts).
- Ability to interpret simulation/measurement results, identify discrepancies, and communicate observations clearly.
- Comfortable working in a Linux/UNIX environment.
- Business level Japanese and English communication skills.
Nice to have
- Exposure to SPICE-based simulation (e.g., Spectre/HSPICE).
- Exposure to mixed-signal environments (Verilog-AMS/Verilog-A).
Skills: SerDes, circuit simulation, silicon bring-up, lab characterization, mixed-signal simulation
This role has been open 145 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | OmniVision | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 2 | 217 |
| Median days open | 145 d | 91 d (+54 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, circuit simulation, silicon bring-up, lab characterization, mixed-signal simulation
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.