Sr Engineer CAD Pre-Silicon Front End - Santa Clara, CA, United States
$200,000 - $300,000 USD yearly
Originally posted 10 September 2026 by the employer.
Own the front end automation that carries our silicon from RTL entry to a clean handoff into DFT and implementation.
About the role
This role involves owning the front end automation for silicon development, spanning RTL entry to handoff for DFT and implementation.
What you'll do
- Own the RTL design flows including build, lint, CDC and formal checks.
- Own register generation and the generator driven flows behind interfaces and integration.
- Own the DV flows including testbench build, regression execution and coverage collection.
- Own emulation and FPGA prototyping build and bring up.
- Build and deploy AI assisted tooling across design and verification workflows.
- Keep design flows available throughout the design cycle, managing tool versions and responding to maintenance requests.
What you'll need
- 8 or more years in design verification, design or CAD engineering, including ownership of a flow area.
- Strong SystemVerilog and RTL fluency with the ability to read and debug design and testbench code.
- Hands on experience building and running simulation and regression flows including testbench compile, coverage collection and results triage.
- Excellent Python skills and a track record of building tools that other engineers maintain.
- Working knowledge of front end design and verification EDA tools from Synopsys, Cadence or Siemens EDA.
- Working knowledge of Linux administration, distributed compute such as LSF or Slurm, and storage and scaling constraints behind large regression workloads.
- Familiarity with databases and dashboarding tools such as Grafana for tracking flow health and regression metrics.
- Track record of supporting a live engineering flow with responsive issue turnaround.
Nice to have
- Experience with UVM, cocotb or Python based verification environments.
- Hands on experience applying LLMs or agentic systems to engineering workflows.
- Experience taking an SoC from RTL bring up through tapeout.
- Experience with emulation and FPGA prototyping platforms such as Palladium, Protium, Veloce or HAPS.
- Experience with retrieval augmented generation, fine tuning or evaluation frameworks for code models.
- Experience at an early stage semiconductor company.
Skills: RTL design flows, lint, CDC, formal checks, DV flows, emulation, FPGA prototyping, EDA tools
This role has been open 35 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 688 |
| Open roles in the wider Physical Implementation family | 6 | 1469 · 108 employers |
| Median days open | 35 d | 78 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: RTL design flows, lint, CDC, formal checks, DV flows, emulation
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.