Sr. Engineer - Analog Validation - Austin, Texas, United States
Originally posted 31 August 2026 by the employer — open 17 days.
Post-silicon validation and characterization for Ambiq’s ultra-low-power SoCs.
About the role
This role is responsible for post-silicon validation and characterization of analog and mixed-signal subsystems within Ambiq’s ultra-low-power SoCs.
What you'll do
- Develop and execute post-silicon validation plans for analog and mixed-signal SoC subsystems.
- Characterize analog IP across process, voltage, temperature, operating modes, and silicon margins.
- Validate performance of analog blocks such as ADCs, DACs, comparators, oscillators, PLLs, references, sensors, regulators, and power management circuits.
- Develop automated test software, embedded firmware, data logging, analysis, and report-generation tools.
- Perform detailed analysis of analog performance including accuracy, linearity, noise, offset, gain, timing, stability, frequency response, and power consumption.
- Debug complex SoC-level issues involving interactions between analog, digital, firmware, clocks, power management, and board-level hardware.
What you'll need
- BS or MS in Electrical Engineering or related field.
- 5+ years of experience in post-silicon validation, analog characterization, mixed-signal validation, or related semiconductor development.
- Strong understanding of analog and mixed-signal circuit behavior and measurement techniques.
- Hands-on experience validating integrated analog blocks such as ADCs, DACs, oscillators, PLLs, references, regulators, or sensor interfaces.
- Experience with oscilloscopes, spectrum analyzers, signal generators, precision DMMs, source measurement units, power supplies, and low-current measurement equipment.
- Experience developing automation using Python, Tcl, C/C++, or similar languages.
- Experience with embedded firmware development and ARM-based MCU or SoC platforms.
Nice to have
- Experience with ultra-low-power SoCs and advanced power management architectures.
- Experience with high-resolution ADC characterization, clocking circuits, PLLs, oscillators, references, and voltage regulation.
- Experience with PVT characterization, shmoo testing, statistical analysis, and specification limit development.
- Experience correlating bench characterization with ATE and production test results.
- Experience with noise analysis, signal integrity, board-level analog design, and precision measurement techniques.
- Familiarity with automated characterization frameworks, Linux development environments, Git, and structured data analysis workflows.
This role has been open 16 days — well below the 27-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
341
|
Median days open
27 d
|
Median salary
$153k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ambiq Micro | All employers we track in this specialty (341 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 341 |
| Open roles in the wider Silicon Validation & Test family | 9 | 1987 · 109 employers |
| Median days open | 22 d | 27 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $153k |
Who's hiring in this category
- Infineon Technologies · 32 open roles · median 26 d
- Renesas Electronics · 32 open roles · median 29 d
- Qualcomm · 23 open roles · median 19 d
- Micron Technology · 22 open roles · median 17 d
- AMD · 18 open roles · median 25 d
- NVIDIA · 16 open roles · median 22 d
How we counted: 341 open Silicon Test Engineering (DFT Test) roles from 66 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.