Sr. EDA Tools Engineer - PERC ESD - United States
$149,600 - $284,580 USD yearly
Originally posted 8 October 2026 by the employer.
Develop PERC ESD rule decks for Intel technologies.
About the role
This role involves developing PERC ESD rule decks within the Design Technology Platform (DTP) organization, enabling design teams to deliver leadership products faster on advanced process technologies.
What you'll do
- Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
- Create and maintain reliability ESD and LU design rule methodologies and specifications.
- Collaborate with internal design, reliability, and CAD teams, and external EDA vendors to define and implement new tool features and requirements.
- Build and execute test cases for rule debugging, validation, and signoff.
- Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.
- Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies.
What you'll need
- Master's degree or PhD in Electrical Engineering or Computer Engineering.
- 2+ years' experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools).
- 2+ years' experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation.
Nice to have
- 4+ years' experience with reliability/DRC tools.
- Industry experience in physical design verification (reliability, device physics, process technology, and design rules, extraction or related domains).
- Strong knowledge of ESD/LU PreSi models (HBM, CDM), I/O design, and related methodologies.
- Experience driving cross functional and industrywide initiatives or task forces.
Skills: PERC ESD rule decks, PDK, reliability verification, scripting, design rule methodologies
This role has been open 2 days — well below the 81-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
690
|
Median days open
81 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (690 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 690 |
| Open roles in the wider Physical Implementation family | 51 | 1470 · 107 employers |
| Median days open | 39 d | 81 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: PERC ESD rule decks, PDK, reliability verification, scripting, design rule methodologies
Who's hiring in this category
- Cadence Design Systems · 160 open roles · median 169 d
- Synopsys · 61 open roles · median 38 d
- Micron Technology · 42 open roles · median 91 d
- Qualcomm · 42 open roles · median 62 d
- NVIDIA · 41 open roles · median 75 d
- GlobalFoundries · 31 open roles · median 52 d
How we counted: 690 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.