Sr Director, Silicon Performance and Design Execution - CA, Santa Clara, United States
Originally posted 30 June 2026 by the employer.
About the role
The Sr Director of Silicon Performance and Design Execution is responsible for owning end-to-end silicon performance and design execution across post-silicon phases. This role provides technical and organizational leadership for system-level performance attainment, hardware/software optimizations, silicon debug, and sustained performance delivery for complex SoCs and accelerators.
What you'll do
- Own end-to-end performance execution for AI/ML workloads, including workload selection, characterization, simulation, performance projection, root-cause analysis, and attainment across pre-silicon and post-silicon phases. - Lead evaluations across LLMs, LDMs, and ranking & recommendation engines to identify key features in DC GPU architectures, software frameworks, and parallelization techniques. - Provide direction for system profiling and analysis to identify performance bottlenecks across rack-scale systems and AI clusters. - Drive strategic architecture features for DC GPU products and guide software optimizations informed by large-scale AI workload analysis. - Manage a global engineering organization of 30+ engineers with growth potential to 50+.
What you'll need
- Bachelor's or Master's degree in Electrical or Computer Engineering. - Demonstrated leadership experience managing engineering teams delivering silicon performance and design execution. - Technical background in system-level performance attainment, hardware/software optimizations, and silicon debug for complex SoCs and accelerators. - Experience aligning cross-functional teams across architecture, design, validation, software, and product engineering.
Nice to have
- Deep experience in Data Center GPU performance architecture spanning compute, memory, and communications for AI workloads. - Expertise in systems architecture, workload modeling, and parallelization techniques in hardware design and software frameworks. - Knowledge of AI software components and frameworks including PyTorch, vLLM, SGLang, JAX, TensorFlow, Transformer Engine, and ONNX.
Skills: silicon performance, HW/SW optimization, SoC architecture, GPU, accelerators
This role has been open 113 days — well above the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
479
|
Median days open
76 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (479 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 479 |
| Open roles in the wider Digital Design & Verification family | 254 | 3283 · 116 employers |
| Median days open | 70 d | 76 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: silicon performance, HW/SW optimization, SoC architecture, GPU, accelerators
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA · 54 open roles · median 71 d
- Apple · 38 open roles · median 14 d
- AMD (this employer) · 35 open roles · median 71 d
- Arm Holdings · 27 open roles · median 119 d
- Micron Technology · 22 open roles · median 111 d
How we counted: 479 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.