Sr. Director of Packaging Engineering - CA, San Jose, United States

Originally posted 8 October 2026 by the employer.

This role focuses on advanced IC packaging technologies, chiplet architectures, and heterogeneous integration.

About the role

This role leads the strategy, development, and execution of advanced IC packaging technologies across AMD's diverse silicon product portfolio. The leader will guide package development from concept through manufacturing ramps, focusing on multi-die and chiplet architectures.

What you'll do

• Champion best practices in design-for-manufacturability, reliability, and cost optimization across the package, SI/PI and thermal/mechanical technology portfolio.
• Own end-to-end packaging development from concept through new product introduction (NPI) and high-volume manufacturing (HVM), including design rules, qualification, and yield/reliability ramp.
• Direct package-level signal integrity and power integrity co-design strategy, including interconnect/channel modeling, power delivery network (PDN) design, impedance control, and high-speed serial/parallel interface optimization for multi-die and chiplet architectures.
• Own thermal and mechanical package design strategy, including thermal simulation and characterization, warpage control, die/package stress management, and thermal-mechanical co-design.
• Participate in strategic relationships with OSAT, substrate, and PWB supply partners, including technology development, qualification, capacity planning, and HVM ramp.

What you'll need

• Significant and progressive experience in semiconductor IC packaging engineering.
• Direct experience developing and qualifying packaging solutions for complex digital, mixed-signal, RF, or high-speed silicon.
• Deep, hands-on technical expertise across advanced and standard packaging technologies, such as WLCSP, flip-chip, chip-on-chip, multi-chip module, system-in-package (SiP), 2.5D/3D integration, or chiplet interconnect.
• Demonstrated expertise in package-level signal integrity engineering, including high-speed interconnect modeling/simulation (S-parameters, channel/eye analysis), crosstalk mitigation, and co-design with SerDes/interface teams.
• Demonstrated expertise in power integrity engineering, including PDN design and analysis, decoupling strategy, IR drop/impedance targets, and co-design with silicon power delivery teams.
• Demonstrated expertise in thermal and mechanical package design, including thermal simulation (e.g., FEA/CFD), thermal interface material (TIM) selection, warpage and stress modeling, and package-level reliability.

Nice to have

• Experience managing OSAT, substrate, and/or PWB supplier partnerships.
• Bachelor's degree in Electrical Engineering, Materials Science, Chemistry, Mechanical Engineering, or a related technical discipline; advanced degree (MS or PhD) preferred.

Skills: advanced IC packaging, design-for-manufacturability, signal integrity, power integrity, thermal/mechanical package design, chiplet architectures