Sr. Design Verification Engineer - CA, Santa Clara, United States
Originally posted 11 September 2026 by the employer.
Work on the distributed services platform, expanding AMD’s data center product portfolio with a high‑performance DPU.
About the role
This role involves driving verification closure on complex, high‑performance ASIC designs, working across IP, subsystem, and SoC levels.
What you'll do
- Develop UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
- Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
- Develop high‑quality SystemVerilog components including stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
- Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
- Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
- Optimize simulations, coverage closure, and verification sign-off methodology.
What you'll need
- Expert‑level knowledge of SystemVerilog and UVM.
- Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
- Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies.
- Strong debug skills across architecture, RTL, and testbench layers.
- Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components.
- Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Nice to have
- Experience with performance verification, power‑aware verification (UPF), or formal verification.
- Familiarity with FPGA/HAPS‑based validation and acceleration flows.
- Understanding of networking or high‑speed I/O pipelines.
- Exposure to architectural modeling or C/C++ reference models.
Skills: UVM-based testbench, SystemVerilog, verification closure, ASIC designs, PCIe/DDR/Ethernet
This role has been open 33 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 97 | 1192 |
| Open roles in the wider Digital Design & Verification family | 255 | 3191 · 115 employers |
| Median days open | 50 d | 65 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM-based testbench, SystemVerilog, verification closure, ASIC designs, PCIe/DDR/Ethernet
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD (this employer) · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.