Sr Design Readiness Engineer - Boise, ID - Main Site, United States
Originally posted 2 September 2026 by the employer.
This role focuses on design readiness activities for new DRAM products.
About the role
This role involves leading design readiness activities, including risk assessments, DFMEA development, and validation planning. You will drive root-cause investigations of silicon findings through data analysis and experiment planning for DRAM products.
What you'll do
- Lead design readiness activities, including risk assessments, DFMEA development, validation planning, and readiness reviews.
- Partner with cross-functional teams to identify product risks, define validation coverage, and prioritize debug activities.
- Drive root-cause investigations of silicon findings through data analysis, experiment planning, evidence review, and corrective action development.
- Influence product readiness decisions by connecting design intent, validation results, silicon behavior, manufacturing constraints, and customer quality expectations.
- Mentor engineers and help improve technical practices, readiness processes, and organizational learning across DRAM programs.
What you'll need
- Advanced degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Applied Physics, Materials Science, or a related technical field, or equivalent industry experience.
- Significant experience in semiconductor design, DRAM or memory technology, silicon validation, product engineering, device characterization, circuit debug, reliability, test development, or new product introduction.
- Proven ability to analyze sophisticated technical problems using silicon data, validation results, circuit behavior, failure analysis, and statistical methods.
- Experience leading technical investigations, root-cause analysis, and cross-functional resolution efforts.
- Strong communication and collaboration skills with the ability to influence technical decisions across engineering organizations.
Nice to have
- PhD or MS in a relevant engineering or scientific field.
- Experience mentoring engineers, leading technical workstreams, or establishing engineering protocols.
- Expertise in silicon debug, screen development, production test coverage, margin characterization, or product quality improvement.
- AI proficiency with experience using approved AI-enabled tools for engineering analysis, user documentation, workflow automation, or knowledge management.
- Experience working with Agentic AI tools to assist with design and verification.
Skills: DRAM products, design readiness, silicon findings, validation planning, circuit debug
This role has been open 32 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM products, design readiness, silicon findings, validation planning, circuit debug
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.