SR ASIC Design Engineer - NoC & AXI Interconnect - CA, Santa Clara, United States
$175,000 - $300,000 USD yearly
Originally posted 19 May 2026 by the employer.
About the role
You will contribute to the ASIC design for high-performance network chips, including AINIC and DPU, as part of the NTSG ASIC Design Team. You will collaborate with architecture, IP design, physical design teams, and product engineers to achieve first-pass silicon success.
What you'll do
- Execute Network-on-Chip (NoC) design and integration. - Deliver AXI, ACE, and APB interface design and verification. - Implement queuing system design and buffer management. - Collaborate with architecture, IP, and physical design teams. - Support post-silicon bring-up and yield learning.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. - Experience with SystemVerilog/Verilog RTL design. - Experience with AXI, ACE, and APB interface design and verification. - Understanding of Network-on-Chip (NoC) architecture, protocols, and design. - Experience with VCS simulation tool and Perl, Python, or Shell scripting. - Knowledge of queuing system design and buffer management.
Skills: Network-on-Chip, NoC, AXI, SystemVerilog, RTL design
This role has been open 158 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 77 | 1084 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 42 d | 63 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Network-on-Chip, NoC, AXI, SystemVerilog, RTL design
Who's hiring in this category
- Qualcomm · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD (this employer) · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.