Spe Applications Validation Engineering - United States
$157,600 - $292,600 USD yearly
Originally posted 5 August 2026 by the employer — open 36 days.
This role focuses on DDR4 and DDR5 memory interface chips.
About the role
This role involves analyzing and debugging complex technical issues related to DRAM, memory interface chips, DIMM, server, and BIOS operation and interaction. You will support international customers of Rambus DDR4 and DDR5 memory interface chips.
What you'll do
- Analyze and debug complex technical issues involving server memory and manage customer issues.
- Support technical qualification of new chip designs to secure customer design wins.
- Assist with validation and debug of new memory interface chips for DDR5 servers.
- Collect and analyze signal integrity data at the system level.
- Conduct failure analysis and prepare failure analysis and 8D reports.
- Prepare technical documentation such as datasheets, user guides, and application notes.
What you'll need
- Familiarity with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers.
- Understanding of signal integrity issues at clock rates of 3 GHz and above.
- Experience with power management and I2C/I3C serial interfaces.
- Extensive experience with probing, using high speed oscilloscopes and other lab equipment.
- History of using fundamental root cause techniques (fishbone, design of experiments, etc.) to solve complex problems.
- Ability to use scripting languages such as Perl, Tcl or Python to analyze data log text files and automate system and bench testing.
- BS degree or higher in Electrical Engineering or related field with 12+ years of experience in hardware design, validation, and/or applications engineering.
Nice to have
- Understanding of ATE tester operation.
- Experience reading and modifying MRC BIOS code and utilizing server platform debug tools (either Intel or AMD).
Skills: DDR5, signal integrity, server memory, high speed oscilloscopes, Perl, Python
This role has been open 153 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Rambus | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 3 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR5, signal integrity, server memory, high speed oscilloscopes, Perl, Python
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.