Software Engineer — RISC-V Random Test Generator
$167,100 - $250,700 USD yearly
Originally posted 1 September 2026 by the employer.
Contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain.
About the role
You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. This framework drives a JIT-style, simulator-coupled generator that produces ELF binaries exercising the RVA23.1 ISA including privileged modes, virtual memory, interrupts, vector, and cryptography extensions.
What you'll do
- Implement new generation objects for RISC-V extensions, common micro-architectural scenarios, and complex data/control-flow composable idioms.
- Add instruction forms and encodings to the python companion assembler and verify bit-level correctness against the RISC-V ISA spec.
- Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
- Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
- Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic.
What you'll need
- 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
- Solid Python 3 skills, comfort with generator-based coroutines and object-oriented design patterns.
- Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model, or similar knowledge for x86 or ARM.
- Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
Nice to have
- Compiler development experience.
- Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.
- Familiarity with constraint-propagation libraries.
- Exposure to random test generation flows or ISS/RTL co-simulation.
Skills: RISC-V, random test generation, RTG, CPU design verification, ISS, RTL verification
This role has been open 43 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 106 | 1187 |
| Open roles in the wider Digital Design & Verification family | 372 | 3192 · 115 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RISC-V, random test generation, RTG, CPU design verification, ISS, RTL verification
Who's hiring in this category
- Qualcomm (this employer) · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.