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SiFive

Software Engineer - FPGA-Accelerated RTL Simulation - Berkeley, California, United States

SiFive Berkeley, California, United States 2 months ago
Digital Design & SoC Architecture

$178,848 - $218,592 USD yearly

Originally posted 17 August 2026 by the employer.

Work on a C++ application for a custom hardware emulation framework based on FireSim.

About the role

This role is responsible for the C++ application that forms the software component of a custom hardware emulation framework.

What you'll do

  • Develop the C++ application for the custom hardware emulation framework.
  • Collaborate with FPGA RTL Designers on Chisel-based FPGA emulators.
  • Work with Compiler Developers on the MLIR & CIRCT-based compiler for ASIC RTL.
  • Build debug tools for co-designing and debugging RISC-V hardware and software.

What you'll need

  • BS/MS/PhD in CS, CE, or EE.
  • 7+ years experience building complete C++ applications.
  • Expertise in modern C++ language features and best practices (C++20 and newer).
  • Strong understanding of C++ concurrency features and experience building multithreaded applications.
  • Self-directed with strong oral and written communication skills.

Nice to have

  • Familiarity with compiler development (LLVM or MLIR).
  • Familiarity with FPGA RTL design.
Market context

This role has been open 60 days — below the 61-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1024
Median days open
61 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How SiFive compares in Digital/RTL Design hiring
Metric SiFive All employers we track in this specialty (1024 roles · 103 employers)
Open roles in this specialty 17 1024
Open roles in the wider Digital Design & Verification family 85 3198 · 115 employers
Median days open 73 d 61 d (+12 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 140 open roles · median 63 d
  • Synopsys · 86 open roles · median 31 d
  • AMD · 71 open roles · median 37 d
  • Analog Devices · 47 open roles · median 49 d
  • NVIDIA · 44 open roles · median 59 d
  • NXP Semiconductors · 42 open roles · median 85 d

How we counted: 1024 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
Berkeley, California, United States
On-site
$178,848 - $218,592 USD yearly
2 months ago

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