$193,000 - $319,000 USD yearly
Originally posted 7 October 2026 by the employer.
About the role
This role involves directing software development to build an AI-driven silicon design platform. The platform will leverage natural language processing, vector databases, knowledge graphs, machine learning pipelines, and retrieval-augmented generation for silicon design insights.
What you'll do
- Own the strategic vision and multi-year roadmap for the AI-driven silicon design platform across NLP, vector databases, knowledge graphs, ML pipelines, and RAG/multi-modal systems.
- Build, lead, and scale an organization of engineering managers and senior engineers, setting technical direction.
- Drive architectural decisions for platform scalability, security, and performance across GPU, cloud, and containerized environments.
- Establish and govern MLOps standards, model lifecycle management, and AI monitoring practices.
- Serve as the executive-level interface between engineering teams and customer-facing stakeholders, prioritizing the roadmap.
- Own the security posture of the platform from the ground up, embedding best practices into the development lifecycle.
What you'll need
- 15 years of experience in Software Engineering, with 5+ years in engineering leadership roles.
- Demonstrated success building and scaling engineering organizations delivering AI/ML-driven platforms in a production environment.
- Strong technical fluency with Python and modern machine learning frameworks.
- Deep understanding of AI platform concepts (transformers, embeddings, fine-tuning, model deployment).
- Experience owning AI inference pipelines or training workflows across cloud environments and containerized platforms at organizational scale.
- Track record of driving large language model strategy across cloud architectures.
- Experience setting engineering standards for Git workflows, containerization, ML pipelines, and automation.
- Strong grounding in vector databases, RAG systems, knowledge graphs, prompt engineering, or AI platform optimization.
- Proven experience partnering with platform architecture teams and driving cross-functional alignment at the executive level.
- Executive-level communication skills.
Nice to have
- Master's or PhD in Computer Engineering, Computer Science, or related field.
- Familiarity with AI-native technologies and platforms (OpenAI, Anthropic, Hugging Face).
- Experience establishing MLOps practices and model automation standards.
- Experience directing retrieval-augmented generation strategy (LangChain, LlamaIndex, or custom RAG architectures).
- Experience in semiconductor, EDA, or related deep-tech industries.
Skills: AI-driven silicon design platform, NLP, vector databases, ML pipelines, RAG
This role has been open 1 day — well below the 34-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
61
|
Median days open
34 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (61 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 61 |
| Open roles in the wider Physical Implementation family | 37 | 1490 · 107 employers |
| Median days open | 1 d | 34 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: AI-driven silicon design platform, NLP, vector databases, ML pipelines, RAG
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 57 d
- Cadence Design Systems · 7 open roles · median 30 d
- Keysight Technologies · 7 open roles · median 9 d
- NVIDIA · 7 open roles · median 29 d
- Qualcomm · 3 open roles · median 46 d
- Altera · 2 open roles · median 10 d
How we counted: 61 open EDA/CAD Engineering (AI EDA Design) roles from 23 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.