SOC Verification and Methodology Engineer -Staff
$140,000 - $210,000 USD yearly
Originally posted 12 August 2026 by the employer.
Join Qualcomm to contribute to IP (block/SoC) development.
About the role
As a Staff SOC Verification and Methodology Engineer, you will define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development. This role focuses on high performance, high quality, low power products.
What you'll do
- Leverage ASIC knowledge and experience to define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
- Create advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate with functional teams to develop and execute an implementation strategy that meets system requirements.
- Evaluate complex process flows from high-level design to synthesis, place and route, timing and power use, and verification.
- Utilize tools/applications such as RTL to GDS Flow and Virtuoso to enable advanced architecture and design of multiple complex blocks/SoC or IC packages.
- Write and review detailed technical documentation for complex EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or a related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 6 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
- 1 year of work experience in a role requiring interaction with senior leadership.
Skills: ASIC design verification, IP (block/SoC) development, system simulations, RTL to GDS Flow, Virtuoso
This role has been open 65 days — slightly above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 1205 |
| Open roles in the wider Digital Design & Verification family | 381 | 3202 · 115 employers |
| Median days open | 38 d | 64 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC design verification, IP (block/SoC) development, system simulations, RTL to GDS Flow, Virtuoso
Who's hiring in this category
- Qualcomm (this employer) · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.