SOC Verification and Methodology Engineer
$164,000 - $246,000 USD yearly
Originally posted 30 June 2026 by the employer.
Qualcomm is hiring an SOC Verification and Methodology Engineer to develop verification infrastructure and drive coverage-based closure for Snapdragon platforms.
About the role
As an SOC Verification and Methodology Engineer, you will be responsible for ensuring the quality and functionality of System-on-Chip (SOC) designs through comprehensive verification processes. You will develop verification methodologies, build test plans, and execute verification suites across IP and system-level integration scopes for Snapdragon platforms.
What you'll do
- Define verification scope from design specifications and develop detailed test plans and verification infrastructure. - Implement and execute verification test cases and debug complex hardware issues. - Implement and analyze System Verilog assertions and coverage metrics, including code, toggle, and functional coverage. - Collaborate with architects, designers, and pre- and post-silicon verification teams across global sites. - Explore verification tools and methodologies to improve testbench quality and verification efficiency.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 6+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 5+ years, or PhD with 4+ years). - Experience with SystemVerilog/UVM based verification skills along with assertion and coverage-based verification methodology. - Experience managing verification flow from test planning to tapeout for large-size hardware designs. - Core proficiency in CPU and ASIC design and verification fundamentals.
Nice to have
- Master's degree in Science, Engineering, or a related field with 15 years of industry experience. - Knowledge of SOC architecture, CPU architecture (ARM), DSP, AMBA Bus, DDR, GPU, and multimedia subsystems. - Exposure to ARM SBSA (Server Base System Architecture) or experience with heterogeneous multi-die system verification and D2D interfaces such as UCIe and CXL. - Experience with pre-silicon emulation platform-based verification and power design/architecture verification. - Experience with scripting languages such as Perl or Python, assertion coding, and formal verification tools.
Skills: ASIC Design Verification, SystemVerilog/UVM, test plans, verification infrastructure, System Verilog assertions, coverage-based verification
This role has been open 116 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 118 | 1259 |
| Open roles in the wider Digital Design & Verification family | 420 | 3310 · 115 employers |
| Median days open | 45 d | 65 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Design Verification, SystemVerilog/UVM, test plans, verification infrastructure, System Verilog assertions, coverage-based verification
Who's hiring in this category
- Qualcomm (this employer) · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.