SoC Power Modeling Engineer
About the role
This role focuses on modeling power dissipation, power delivery, peak current requirements, and voltage-frequency operating points for various IPs across Apple SOCs. You will work across architecture, design, thermal, PMIC, and validation teams to correlate power models with hardware data.
What you'll do
- Model power dissipation and power delivery across SOC power rails.
- Establish voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, AI/ML compute accelerators, media IPs, caches, and fabric.
- Model power dissipation for customer use-cases.
- Interact with Technology, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre- and post-silicon.
- Work with the power lab and test teams to correlate models to hardware data.
What you'll need
- Bachelor's degree in a relevant field.
- Minimum of 3 years of relevant industry experience.
Nice to have
- Understanding of SOC power modeling and current demand.
- Understanding of electrical properties of on-die PDN, power gating, package, and system power delivery.
- Skills in scripting, data analysis, and experience with EDA tools.
- Understanding of VLSI design flow and CMOS technology.
- Extensive background in EE.
- Ability to understand and model thermal control loops and throttling mechanisms.
- Familiarity with physical design tools for power optimization.
Skills: power modeling, DVFS, SoC architecture, PDN, low power
More semiconductor jobs: SoC design jobs
This role has been open 0 days — well below the 74-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
484
|
Median days open
74 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (484 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 484 |
| Open roles in the wider Digital Design & Verification family | 172 | 3381 · 114 employers |
| Median days open | 24 d | 74 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: power modeling, DVFS, SoC architecture, PDN, low power
Who's hiring in this category
- Qualcomm · 77 open roles · median 87 d
- NVIDIA · 62 open roles · median 75 d
- Apple (this employer) · 48 open roles · median 22 d
- AMD · 39 open roles · median 62 d
- Arm Holdings · 30 open roles · median 5 d
- Micron Technology · 21 open roles · median 109 d
How we counted: 484 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.