SOC Power/Limits Architect
$145,600 - $218,400 USD yearly
Originally posted 21 September 2026 by the employer.
This role focuses on designing a holistic Limits Management architecture.
About the role
You will design a holistic Limits Management architecture.
What you'll do
- Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors.
- Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for mitigation strategies.
- Drive organizational consensus on feature ROI and oversee Post-Silicon Validation.
- Help with post silicon power correlation to match with pre-silicon power models and simulations.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years, OR PhD in Science, Engineering, or related field and 2+ years.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- MS or PhD in Electronics or Computer Engineering, or equivalent with focus on computer architecture and power/performance analysis.
- 6 years of ASIC design, verification, validation, integration, or related work experience (5 years if Master’s; 4 years if PhD).
- Experience with power management and low-power design methodologies.
- Strong C/C development skills for architectural modeling and FW prototyping, alongside Python for data analysis, performance profiling, and workflow automation.
Skills: SoC Limits Management architecture, silicon health, Power Telemetry, Post-Silicon Validation, power correlation
This role has been open 20 days — well below the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
455
|
Median days open
78 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (455 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 74 | 455 |
| Open roles in the wider Digital Design & Verification family | 386 | 3171 · 114 employers |
| Median days open | 83 d | 78 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: SoC Limits Management architecture, silicon health, Power Telemetry, Post-Silicon Validation, power correlation
Who's hiring in this category
- Qualcomm (this employer) · 74 open roles · median 82 d
- NVIDIA · 58 open roles · median 65 d
- AMD · 34 open roles · median 60 d
- Apple · 34 open roles · median 5 d
- Arm Holdings · 27 open roles · median 108 d
- NXP Semiconductors · 21 open roles · median 110 d
How we counted: 455 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.