SoC Power Analysis and Optimization Engineer
About the role
This role is responsible for SoC power simulation, optimization, and modeling within the Silicon Engineering group.
What you'll do
- Work with cross-functional teams, including architecture, RTL, and physical design teams, to determine use-cases to simulate power, provide power projections and targets for future projects, and improve SoC power efficiency.
- Drive power analysis and optimization tasks with SoC power team members, improving efficiency with automation and GenAI/LLM approaches.
- Explore new methodology to analyze power data, create power metrics to identify optimization opportunities, and drive automated approaches to improve SoC power efficiency across IPs.
- Collaborate with cross-functional teams to deploy power optimization, review results, and improve methodology runtime and design scope support.
What you'll need
- Bachelor's degree in a relevant field.
- Minimum of 3 years of relevant industry experience.
Nice to have
- Familiarity with ASIC power analysis and optimization.
- Familiarity with machine learning algorithms and programming.
- Familiarity with Verilog and System Verilog.
- Familiarity with SoC design flow and methodology.
- Familiarity with scripting in Python.
- Familiarity with computer architecture, logic and circuits design.
- Familiarity with signal processing.
- Silicon power measurement experience.
- SoC power modeling, low power design, and power optimization experience.
Skills: ASIC power analysis, power optimization, Verilog, System Verilog, SOC design flow, low power design
More semiconductor jobs: RTL design jobs
This role has been open 87 days — well above the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1057
|
Median days open
60 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1057 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 1057 |
| Open roles in the wider Digital Design & Verification family | 168 | 3376 · 114 employers |
| Median days open | 16 d | 60 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC power analysis, power optimization, Verilog, System Verilog, SOC design flow, low power design
Who's hiring in this category
- Qualcomm · 139 open roles · median 69 d
- Synopsys · 85 open roles · median 46 d
- AMD · 81 open roles · median 47 d
- NXP Semiconductors · 44 open roles · median 101 d
- Analog Devices · 42 open roles · median 48 d
- NVIDIA · 41 open roles · median 69 d
How we counted: 1057 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.