SoC Physical Integration Engineer - CA, San Jose, United States
$103,600 - $177,600 USD yearly
Originally posted 10 June 2026 by the employer. Relisted by the employer on 15 October 2026.
About the role
As a member of the SoC Physical Integration team, you will contribute to the physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices. The role focuses on products within AMD's Adaptive Embedded Computing Group (AECG).
What you'll do
- Define and develop flows and methodologies for chip-level integration. - Develop tools and automation to enhance design verification and engineering efficiency. - Design, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design. - Coordinate activities across design teams to enable seamless chip-level integration. - Execute chip-level physical verification. - Execute chip-level electrical verification.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field. - Experience with chip-level physical verification and electrical verification flows. - Experience with RTL and custom design integration. - Experience working in Unix/Linux environments, including data management and job control.
Nice to have
- Solid understanding of FPGA architectures. - Hands-on experience with advanced process nodes, including 2nm and 3nm technologies. - In-depth knowledge of 2.5D and 3D interposer technologies. - Hands-on experience with physical implementation using tools such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools. - Circuit design foundation with hands-on simulation experience using SPICE and Verilog. - Knowledge of or practical experience with Place and Route (P&R) tools and methodologies. - Proficiency in scripting languages such as Perl, Python, TCL, C-shell, or Make.
Skills: chip level integration, physical verification, electrical verification, Virtuoso, Calibre, Place and Route
This role has been open 181 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
676
|
Median days open
66 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (676 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 676 |
| Open roles in the wider Physical Implementation family | 89 | 1513 · 111 employers |
| Median days open | 28 d | 66 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: chip level integration, physical verification, electrical verification, Virtuoso, Calibre, Place and Route
Who's hiring in this category
- Qualcomm · 123 open roles · median 49 d
- AMD (this employer) · 63 open roles · median 28 d
- Intel Corporation · 40 open roles · median 18 d
- Synopsys · 37 open roles · median 40 d
- NVIDIA · 36 open roles · median 68 d
- Broadcom · 35 open roles · median 105 d
How we counted: 676 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.