SoC Performance Architect (Server CPU) - PhD New Grads Welcome! - Santa Clara, California, United States of America
$142,200 - $213,200 USD yearly
Originally posted 21 July 2026 by the employer.
About the role
This role leads server CPU workload analysis, performance modeling, competitive projection, and optimization across hardware and software. It focuses on end-to-end system performance for complex server workloads, identifying bottlenecks across CPU, memory, interconnect, I/O, firmware, OS, compiler, and application layers.
What you'll do
- Define performance methodologies, metrics, and KPI frameworks for consistent workload tracking and feature evaluation. - Perform bottleneck analysis across CPU cores, cache hierarchy, memory subsystem/controllers, on-chip fabric, and I/O. - Use profiling and PMU tools to capture hotspots, call stacks, CPI breakdowns, memory behavior, and microarchitectural stall data. - Build analytical and empirical models for workload behavior, scaling, and feature sensitivity. - Conduct hardware/software sensitivity studies and develop performance projections for internal roadmap products and external competitors. - Identify optimization opportunities and drive execution across architecture, design, compiler, OS, firmware, and application teams.
What you'll need
- Bachelor's degree with 2+ years of experience, Master's with 1+ year, or a PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field. - 2+ years of experience in system architecture technology areas and products (such as Power System, Shared Resource Management, Limits/Thermal Management, or Hardware Islands). - Deep understanding of CPU microarchitecture, including pipelines, out-of-order execution, branch prediction, caches, prefetching, SMT, and performance bottlenecks. - Strong knowledge of SoC architecture, including on-chip interconnect/fabric, memory controllers, DRAM systems, coherency, and I/O subsystems. - Hands-on experience with industry-standard performance analysis and profiling tools, plus experience debugging complex server workloads in Linux environments. - Understanding of OS and compiler behavior, including scheduling, memory management, synchronization, code generation, and optimization. - Scripting and data analysis skills for handling large profiling datasets and developing performance models.
Nice to have
- Experience with pre-silicon performance modeling, simulation, or trace-based analysis. - Familiarity with PMU-based top-down analysis, CPI decomposition, memory subsystem analysis, and sensitivity modeling.
Skills: CPU microarchitecture, SoC architecture, performance modeling, bottleneck analysis, workload characterization
This role has been open 89 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
78 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 73 | 472 |
| Open roles in the wider Digital Design & Verification family | 392 | 3224 · 116 employers |
| Median days open | 89 d | 78 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: CPU microarchitecture, SoC architecture, performance modeling, bottleneck analysis, workload characterization
Who's hiring in this category
- Qualcomm (this employer) · 73 open roles · median 89 d
- NVIDIA · 56 open roles · median 70 d
- Apple · 36 open roles · median 13 d
- AMD · 34 open roles · median 61 d
- Arm Holdings · 27 open roles · median 116 d
- Micron Technology · 22 open roles · median 108 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.