$174,400 - $261,600 USD yearly
Originally posted September 10, 2026 by the employer.
About the role
As an SoC Limits Management Architect on the HW power team, you will define how systems balance performance against physical, electrical, and thermal constraints. You will bridge hardware IP, system software, and product requirements to design architecture and micro-architecture solutions across the product life cycle.
What you'll do
- Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across IP and hardware blocks.
- Drive the evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address current densities and industry trends.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for mitigation strategies.
- Oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 15 years of industry experience in Power Management or Low-Power Design/Methodology (or at least 6+ years of ASIC design, verification, validation, integration, or related work experience).
- Experience navigating the full product delivery cycle, from initial architecture definition through post-silicon productization.
- Experience with low-power architectures and advanced power optimization techniques.
Nice to have
- MS or PhD in Electronics or Computer Engineering with a focus on computer architecture and power/performance analysis.
- Experience in peak power management, power budgeting, in-rush current, PDN droop detection and mitigation, and adaptive clock distribution.
- Experience with aging and process monitors, power aware floorplanning, battery technology, concurrency management, thermal management, and AI.
Skills: limits management, micro-architecture, power management, PDN droop, thermal management
More semiconductor jobs: Qualcomm jobs · SoC design jobs · San Diego jobs
First seen in our index 64 days ago, below the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
520
|
Median days since first seen
72 d
|
Category median salary (all employers)
$228k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (520 roles · 70 employers) |
|---|---|---|
| Open roles in this specialty | 94 | 520 |
| Open roles in the wider Digital Design & Verification family | 454 | 3639 · 122 employers |
| Median days since first seen | 66 d | 72 d (+6 d vs this employer) |
| Median salary (USD postings) | n/a | $228k |
Skills observed across this category: limits management, micro-architecture, power management, PDN droop, thermal management
Who's hiring in this category
- Qualcomm (this employer) · 92 open roles · median 73 d
- NVIDIA · 69 open roles · median 86 d
- AMD · 41 open roles · median 72 d
- Apple · 40 open roles · median 14 d
- Arm Holdings · 28 open roles · median 17 d
- Micron Technology · 21 open roles · median 113 d
How we counted: 520 open SoC/Chip Architecture (SOC Architecture) roles from 70 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.