SOC Integration Engineer - Mountain View, CA, United States
$275,000 - $600,000 USD yearly
Originally posted 27 May 2026 by the employer.
About the role
The SOC Integration Engineer develops scalable integration flows and full-chip SOC top-level RTL, bridging silicon architecture and physical design implementation. The role focuses on delivering performant compute, memory management, and high-speed interconnect implementations such as UCIE for GenAI workloads.
What you'll do
- Build scalable solutions to integrate subsystems into full-chip SOC RTL designs and partner with subsystem owners on block integration.
- Implement automation for top-level RTL integration and build flows to enable on-the-fly generation of SOC top-level RTL.
- Collaborate with physical design to incorporate feedthroughs, highways, and floorplan connectivity requirements into the SOC RTL.
- Establish clock and reset methodologies across system, architecture, design, and physical design teams.
- Define and validate SoC-level timing constraints against subsystem and physical design requirements.
- Support package and board engineering by defining SOC pin requirements and facilitating interposer netlist generation.
What you'll need
- Proficiency in SystemVerilog and scripting languages including Python or Perl for chip design RTL and automation flows.
- Experience integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards including UCIE.
- Working knowledge of logical equivalency verification, memory wrapper generation, and DFT wrapper integration into subsystem RTL.
- Hands-on experience with design synthesis, linting, clock and reset-domain-crossing (CDC/RDC), and timing constraint validation.
- Experience generating and configuring SOC RTL test configurations for Design Verification (DV).
Skills: silicon architecture, SOC RTL design, subsystem integration, clock and reset methodologies, timing constraints, UCIE
This role has been open 149 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
78 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MatX | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 473 |
| Open roles in the wider Digital Design & Verification family | 30 | 3328 · 115 employers |
| Median days open | 116 d | 78 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: silicon architecture, SOC RTL design, subsystem integration, clock and reset methodologies, timing constraints, UCIE
Who's hiring in this category
- Qualcomm · 80 open roles · median 82 d
- NVIDIA · 52 open roles · median 69 d
- Apple · 37 open roles · median 16 d
- AMD · 36 open roles · median 73 d
- Arm Holdings · 27 open roles · median 121 d
- Micron Technology · 21 open roles · median 100 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.