SoC HW Architecture - San Diego, California, United States of America
$148,300 - $222,500 USD yearly
Originally posted 6 May 2026 by the employer.
Define SoC infrastructure HW architecture spanning NOC, System Cache, SMMU, and UCIe or Die-to-Die chiplet interconnects.
About the role
This position involves defining hardware architecture for SoC infrastructure hardware IPs, including interconnect (NOC), system cache, memory controllers, and system MMU. The role focuses on architecture definition based on product requirements, HW-SW interfaces, and multi-die chiplet links with ARM architecture.
What you'll do
- Define hardware architecture for SoC infrastructure hardware IPs, including NOC, system cache, memory controllers, and System MMU. - Define HW architectures based on product requirements and developer-friendly HW-SW interfaces. - Perform HW-and-SW feature trade-offs across the end-to-end silicon hardware design flow. - Architect multi-die and chiplet systems utilizing Die-to-Die and Chip-to-Chip links. - Define architecture for Quality of Service, clocks, power management, security, and debug components. - Conduct performance modeling, validation, and support RTL design flows.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years of systems engineering or related experience (or Master's with 3+ years, or PhD with 2+ years). - 2+ years of experience in system architecture technology areas and products (such as power systems, shared resource management, limits/thermal management, or hardware islands). - Hands-on experience with multi-die / chiplet architectures and Die-to-Die or Chip-to-Chip links. - Knowledge of industry standard Interconnect Protocol and IO Devices Protocol. - Knowledge of SoC and infrastructure IP HW architecture, including NOC, SMMU, and caches. - Experience with HW-SW interfaces, firmware, performance modeling, and RTL design flows.
Nice to have
- Knowledge of SoC infrastructure IP including Memory Controller and Interrupt Handler. - Experience with Platform System Architecture such as ARM, X86, or RISC-V. - Experience with industry protocols including PCIe, CXL, USB, UFS, MIPI, and UCIe. - Knowledge of ARM Advanced Technology in Security, RAS, MPAM, and Memory Tagging. - Experience in Functional Safety, Data Science, or Machine Learning.
Skills: multi-die architectures, chiplet, Die-to-Die, Interconnect Protocol, SOC, Infrastructure IP
This role has been open 171 days — well above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
477
|
Median days open
79 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (477 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 80 | 477 |
| Open roles in the wider Digital Design & Verification family | 424 | 3328 · 115 employers |
| Median days open | 83 d | 79 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: multi-die architectures, chiplet, Die-to-Die, Interconnect Protocol, SOC, Infrastructure IP
Who's hiring in this category
- Qualcomm (this employer) · 80 open roles · median 83 d
- NVIDIA · 56 open roles · median 67 d
- Apple · 37 open roles · median 17 d
- AMD · 36 open roles · median 74 d
- Arm Holdings · 27 open roles · median 122 d
- Micron Technology · 21 open roles · median 101 d
How we counted: 477 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.