SOC Engineering, Senior Engineer
Originally posted 6 October 2026 by the employer.
Work on SoC designs incorporating AXI, APB, and AHB protocols.
About the role
This Senior Engineer role focuses on SOC engineering, designing digital logic that synthesizes and meets timing requirements.
What you'll do
- Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers.
- Run RTL quality checks using tools like linting, CDC/RDC analysis, and synthesis before handoff to physical design.
- Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps.
- Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure.
- Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems.
- Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3 to 4 years of hands-on experience in ASIC or FPGA RTL design, implementation, and debug.
- Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs.
- Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure.
Nice to have
- Experience using industry-standard tools such as simulators, lint checkers, CDC/RDC analysis tools, synthesis tools, and static timing analysis.
- An understanding of standard interface protocols including AXI, APB, AHB, I2C, and SPI.
- Experience with PCIe, DDR, or Ethernet protocols.
- Familiarity with SystemVerilog assertions, C++, or Python for verification or scripting tasks.
- Familiarity with low-power design methodologies and UPF.
- Familiarity with DFT requirements.
- Familiarity with Git-based development flows.
- Familiarity with formal verification tools or AI-assisted engineering tools and code-generation assistants.
Skills: RTL code, Verilog, SystemVerilog, ASIC design flow, synthesis, timing closure
This role has been open 1 day — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1010
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1010 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 86 | 1010 |
| Open roles in the wider Digital Design & Verification family | 167 | 3177 · 113 employers |
| Median days open | 23 d | 62 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL code, Verilog, SystemVerilog, ASIC design flow, synthesis, timing closure
Who's hiring in this category
- Qualcomm · 143 open roles · median 60 d
- Synopsys (this employer) · 82 open roles · median 24 d
- AMD · 73 open roles · median 35 d
- Analog Devices · 48 open roles · median 40 d
- NXP Semiconductors · 48 open roles · median 77 d
- NVIDIA · 45 open roles · median 63 d
How we counted: 1010 open Digital/RTL Design (RTL Design) roles from 97 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.