SoC Engineering, Principal Engineer-18586
Originally posted 28 September 2026 by the employer.
This role focuses on delivering high-performance digital IP subsystems.
About the role
This role involves leading the design and development of complex ASIC digital subsystems from concept to silicon. You will be defining architecture and delivering high-quality RTL for robust, scalable subsystem designs.
What you'll do
- Lead the subsystem lifecycle from requirements and architecture definition through release.
- Develop subsystem architecture, functional specifications, and high-quality RTL micro-architecture.
- Drive design quality through RTL linting, CDC, RDC, and partnership with verification, DFT, and implementation teams.
- Integrate standard protocols such as UCIe, Ethernet, UALink, and AMBA into subsystem designs.
- Apply low power and DFT design methodologies at the architectural level.
- Mentor junior engineers and contribute to technical reviews and design excellence.
What you'll need
- BSEE, BSCE, MSEE, MSCE, or an advanced degree, plus 8+ years of direct experience in RTL design and subsystem architecture for complex ASIC or SoC projects.
- Strong expertise in RTL coding using Verilog/System Verilog, along with linting, CDC, RDC, and formal verification tools.
- Experience with standard protocols such as UCIe, Ethernet, UALink, and AMBA.
- Solid knowledge of low power design methodologies, DFT architecture, and the broader ASIC design flow.
- Proven ability to lead cross-functional efforts from specification through silicon.
Skills: subsystem architecture, RTL micro-architecture, low power design, DFT architecture, UCIe
This role has been open 9 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
460
|
Median days open
77 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (460 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 460 |
| Open roles in the wider Digital Design & Verification family | 167 | 3183 · 114 employers |
| Median days open | 6 d | 77 d (−71 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: subsystem architecture, RTL micro-architecture, low power design, DFT architecture, UCIe
Who's hiring in this category
- Qualcomm · 76 open roles · median 81 d
- NVIDIA · 60 open roles · median 64 d
- AMD · 36 open roles · median 59 d
- Apple · 34 open roles · median 4 d
- Arm Holdings · 27 open roles · median 107 d
- NXP Semiconductors · 21 open roles · median 109 d
How we counted: 460 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.