SoC Engineering, Principal Engineer
Originally posted 5 October 2026 by the employer.
About the role
This Principal Engineer role involves leading design teams through the full ASIC and FPGA development cycles, from specification to GDSII handoff, and architecting complex SoC designs from customer requirements.
What you'll do
- Lead design teams through full ASIC and FPGA development cycles, from specification to GDSII handoff.
- Partition and architect complex SoC designs, creating high-level and micro-architectures balancing performance, area, and power.
- Drive RTL development using SystemVerilog, ensuring quality through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness.
- Collaborate with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements.
- Implement industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SoC designs.
- Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff.
What you'll need
- Bachelor's degree in Electrical Engineering or Computer Engineering.
- 15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases.
- Proven experience leading design teams, including mentoring engineers and managing technical execution.
- Deep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical design handoff.
- Strong SystemVerilog RTL coding skills with demonstrated ability to design and review complex control and datapath logic.
- Working knowledge of industry-standard protocols such as PCIe, Ethernet, or UCIe in real production designs.
- Experience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms.
Skills: micro-architecture, RTL development, ASIC, FPGA, timing closure
This role has been open 2 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 461 |
| Open roles in the wider Digital Design & Verification family | 167 | 3175 · 113 employers |
| Median days open | 6 d | 76 d (−70 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: micro-architecture, RTL development, ASIC, FPGA, timing closure
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.