SOC Engineering, Architect- 19169
Originally posted 7 October 2026 by the employer.
About the role
This role involves defining and integrating subsystem architectures, ensuring proper interoperability and compatibility with SoC-level interconnects and firmware requirements. You will work on IP subsystems that power automotive AI and 5G infrastructure.
What you'll do
- Define subsystem architectures for memory controllers, interconnect clusters, compute blocks, power management units, or communication subsystems.
- Integrate multiple IP blocks into cohesive subsystems, ensuring proper interoperability and interface compatibility.
- Lead architecture exploration activities including IP selection, subsystem modeling, and validation of candidate architectures.
- Coordinate with SoC architects, verification teams, software engineers, and physical design groups to ensure subsystem feasibility.
- Define verification requirements for subsystem functionality, performance, power states, and protocol compatibility.
- Produce architecture documents, subsystem specifications, engineering guidelines, and implementation requirements.
What you'll need
- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 15+ years of overall semiconductor experience.
- 10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles.
- Deep expertise in Verilog and SystemVerilog for RTL design and simulation, with hands-on experience using industry-standard simulation tools.
- Strong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol-level debugging and performance analysis.
- Experience with synthesis, lint, CDC, low power design flows, and verification closure using SystemVerilog UVM, BFM development, or test environment creation.
- Demonstrated ability to coordinate cross-disciplinary teams including hardware, firmware, software, verification, and physical design groups.
Skills: subsystem architectures, memory controllers, interconnect clusters, AMBA AXI, DDR, PCIe
This role has been open 0 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 461 |
| Open roles in the wider Digital Design & Verification family | 167 | 3195 · 113 employers |
| Median days open | 6 d | 76 d (−70 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: subsystem architectures, memory controllers, interconnect clusters, AMBA AXI, DDR, PCIe
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.