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Synopsys

Soc Engineer (Physical Design)

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Ho Chi Minh City, Vietnam 13 days ago
Physical Design & EDA

Originally posted 22 September 2026 by the employer.

About the role

This role involves developing and implementing SoC designs using Synopsys EDA tools and IP, covering all stages from Verilog to GDS.

What you'll do

  • Develop and implement SoC designs using Synopsys EDA tools and IP.
  • Contribute to turnkey projects and advise customer design and CAD teams.
  • Innovate solutions to problems independently with occasional guidance.
  • Set task-level goals and consistently meet schedules.
  • Collaborate with other Synopsys teams to deploy tool and IP solutions.
  • Provide technical guidance and mentorship to junior team members.

What you'll need

  • BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
  • 5 to 10 years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.
  • Strong debugging skills and a good understanding of P&R, extraction, timing, IREM, and Physical Verification fundamentals.
  • Proficiency in TCL/PERL scripting.

Skills: Place & Route, Fusion Compiler, ICC2, timing, Physical Verification, TCL, PERL

Market context

This role has been open 0 days — well below the 61-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
630
Median days open
61 d
Median salary
$187k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Physical Design hiring
Metric Synopsys All employers we track in this specialty (630 roles · 78 employers)
Open roles in this specialty 28 630
Open roles in the wider Physical Implementation family 88 1417 · 108 employers
Median days open 57 d 61 d (−4 d vs this employer)
Median salary (USD postings) — $187k

Skills observed across this category: Place & Route, Fusion Compiler, ICC2, timing, Physical Verification, TCL

Who's hiring in this category

  • Qualcomm · 123 open roles · median 37 d
  • NVIDIA · 39 open roles · median 48 d
  • Broadcom · 38 open roles · median 73 d
  • AMD · 35 open roles · median 43 d
  • Synopsys (this employer) · 27 open roles · median 62 d
  • Cadence Design Systems · 23 open roles · median 87 d

How we counted: 630 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Ho Chi Minh City, Vietnam
On-site
13 days ago

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