SoC DRAM Memory Subsystem Validation Engineering Program Manager - San Diego, United States

Originally posted 14 July 2026 by the employer. Relisted by the employer on 29 September 2026.

About the role

This role drives memory subsystem readiness, bring-up, validation, and debug for custom SoCs. You will serve as the technical interface between DRAM architecture, memory controller design, design verification (DV), DDR PHY, DRAM product engineering, and software teams.

What you'll do

- Manage bring-up, validation, and debug for high-bandwidth multi-client memory subsystems across Apple SoC product lines. - Coordinate execution across DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams from architecture through mass production. - Drive DRAM industry mobile roadmap definition and evaluate DRAM technologies for integration into custom SoCs. - Lead resolution of critical technical problems under pressure and implement real-time crisis management during bring-up and validation phases. - Track project milestones using well-defined metrics and prepare executive reporting on validation and debug progress.

What you'll need

- BS degree with 20+ years of relevant experience. - Direct experience in SoC DRAM memory design, validation, architecture, or test/product engineering. - Demonstrated technical debugging skills and ability to extract action plans from complex technical discussions. - Proven experience driving critical problem resolution under tight schedule constraints.

Nice to have

- Knowledge of high-performance memory subsystems, including SoC memory architecture, DDR controller, PHY design, high-speed IO interface, DRAM devices, and calibration/training mechanisms. - Experience shipping high-volume DRAMs or SoCs. - Previous experience working with major DRAM memory vendors and validation of DRAM devices.

Skills: Program Manager, DRAM Memory Subsystem, SoC memory architecture, DDR controller, high-speed IO interface